LABORATORY

Lab Assistant: Alaa ELEYAN,  e-mail: alaa.eleyan@emu.edu.tr, Ext.: 2774
 

Lab results and makeup schedules are posted! (see the Announcements section)


 
   Some Important Notes:
  1. Lab sheets will be handed out to you at the beginning of each session.
  2. The experiments will be carried out in groups of 3 students.
  3. There is no need to submit a Lab report. Answering the specified questions, however, is required and your Lab performance will be evaluated accordingly.
  4. Participation is mandatory. Marks will be deducted from those students who do not participate during the sessions.
  5. Experiments are in multi-task format. Upon completion of each task, groups must demonstrate their obtained results by operating their constructed circuitries.
  6. Since, at the beginning of each session, a short introduction will be given on new topics, late students are NOT allowed to join the classroom. Therefore, try your best to be on time.
  7. If you happen to miss any sessions, you may still attend the Lab with the consequent groups during that week. This, however, is not recommended since the groups are usually packed.
  8. There will be only ONE makeup Lab available to those students who have missed a session. Other students who have already attended all the experiments are NOT allowed to enter the makeup.
  9. If you miss more than one session, you will receive zero for what you have not attended, excluding the makeup. The makeup lab will then compensate for one of your absences. On the other hand, if you miss more than three sessions you will automatically receive zero for your total lab grade.
  10. Students who obtain zero from the lab, will receive the letter "F" as their course grade regardless of their performance! Therefore, it is strongly recommended to attend all the laboratory sessions.


 
 

EENG 211 DESCRIPTION OF LAB. EXPERIMENTS
 

Experiment 1:  TTL LOGIC GATES

Objective:

            To demonstrate the operation and characteristics of a TTL logic gate and to show how it can be used to perform any of three basic logic functions. 

Apparatus:

            SN7400N (7400) quad-two input TTL integrated circuits

            1N4149 silicon diode (56-56)

            560ohm ½ watt resistor

            Heathkit ET-3200 Digital Design Experimenter

            DC Voltmeter      

Description:

            The operational characteristics of TTL logic gates are studied.  This is done by the use of TTL, NAND gate, which is also used to implement the three basic logic gates (NOT, OR, AND) functions. Students will understand how such basic gates can be implemented by the use of the available NAND gate. The TTL logic gate performs NAND function in positive logic while it performs NOR function in negative logic.     

 

Experiment 2:  CMOS LOGIC GATES

Objective:

            To demonstrate the operation and characteristics of a CMOS logic gate and to show how it can be used to perform any of the three basic logic functions. 

Apparatus:

            CD4001AE (4001) quad-two input CMOS integrated circuit

            Heathkit ET-3200 Digital Design Experimenter

            DC Voltmeter      

Description:

            The operational characteristics of CMOS logic gates are studied.  This is done by the use of CMOS, NOR gate, which is also used to implement the three basic logic gates (NOT, OR, AND) functions. The CMOS logic gate performs NOR function in positive logic while it performs NAND function in negative logic.     



Experiment 3:  APPLYING NAND, NOR & XOR GATES

Objective:

            To show how TTL and CMOS, NAND and NOR gates are used to implement any logic function and to demonstrate the value of Boolean algebra in reducing logic circuits to their minimum configuration. To demonstrate the operation of exclusive OR and exclusive NOR gates.        

Apparatus:

            Heathkit ET-3200 Digital Design Experimenter

            7400 TTL  IC.

            7420 TTL  IC.

            7402 TTL  IC.

            7486 IC.

            4001 CMOS IC.                         

Description:

            TTL NAND and NOR gates are used to implement logic functions. Starting from the Boolean expression, the corresponding logic circuit is designed and implemented without simplification then by means of Boolean algebra this Boolean expression can be simplified, designed and then implemented. This will demonstrate the importance of the Boolean algebra in minimizing the equation and the hardware. Students can compare the logical operation of the two circuits.
            An exclusive OR circuit is constructed by the use of a 7400 quad two input NAND gate. Its logical operation is verified to be equivalent to that for Exclusive OR gate. Practical application of exclusive OR gates can be the binary buffer /complementor circuit. In this circuit, four bit binary word from the data switches is applied to the four exclusive OR gates and one input of each of the exclusive ORs is connected together and wired to logic switch A, (control), if A is binary 0 the circuit works as buffer (outputs same as inputs) however if A is binary 1 the circuit works as complementor. 

          

Experiment 4:  DECODERS & MULTIPLEXERS

Objective:

To demonstrate the operation of decoders and digital multiplexer       

Apparatus:

            Heathkit ET-3200 Digital Design Experimenter

            7400 IC.

            7404 IC.

            7420 IC.

            7442 IC.

            74151 IC.

            74193 IC.

            1KW resistor                                             

Description: 

In the first step 2 x 4 decoder is designed and implemented by the use of two input NAND gates with or without output invertors and the operational characteristic of this decoder is studied. In the second step 7442 BCD to decimal decoder is used to illustrate BCD to decimal conversion.
           2-input multiplexer or data selector circuit is constructed and its operation is evaluated then a binary counter is used to select one of eight inputs on the 74151 multiplexer. The binary code from the counter is decoded within the multiplexer and enables one of the eight input lines. The decimal value of the input line enabled corresponds to the equivalent binary input code.

 

Experiment 5: SET –RESET FLIP FLOPS

Objective:

            To demonstrate the operation and characteristics of a set–reset (latch) flip-flop.

Apparatus:

            Heathkit ET-3200 Digital Design Experimenter

            7400 IC.

            7402 IC.

Description:

            A NAND gate latch and a NOR gate latch are constructed by the use of 7400 and 7402 ICs respectively. Operations of the two types of latches are evaluated. In comparison, either type flip-flop will store one bit of data, with the state of the outputs indicating the value of the bit stored. The two outputs are complementary. The NAND latch requires a low level on either input to set or rest it, however the NOR latch requires a high level at the appropriate input to change its state. Both type of latches have an ambiguous state. In the NAND both outputs are high. In the NOR both outputs are low.

 

Experiment 6:  BINARY COUNTERS

Objective:

            To demonstrate the operation and characteristics of a binary counter     

Apparatus:

            Heathkit ET-3200 Digital Design Experimenter

            DC voltmeter

            7476 dual JK Flip-flop IC

            74193 synchronous up/down binary counter IC

            l kW resistor

  Description:

       A four bit binary counter is constructed using JK flip-flops. This is a binary up counter of asynchronous or ripple type since the normal output of one flip-flop is connected to the toggle (T) input of the next flip-flop. By stepping the counter with logic switch (A) we observe that the count sequence of the counter is from 0000 to 1111. A binary down counter can be constructed by connecting the complement output of each of the flip-flop to the T input of the next in sequence. The 74193 is a TTL MSI up / down counter it operates synchronously and can be preset (parallel loaded) from an external 4-bit data source.

 

Experiments 7-8:  SOFTWARE SIMULATION (TINA)

Objective:

       To simulate the experiments carried out previously and to get familiarized with design (and other) capabilities of simulation software.

 

The above program is subject to change